The field of this invention relates to an analog-to-digital converter (ADC) circuit, an integrated circuit, an electronic device such as a wireless communication unit and a method for managing an ADC overload condition. The invention is applicable to, but not limited to, an integrated circuit comprising an ADC for a wireless communication unit's modem application.
In the field of wireless communication systems and communication units, which comprise both transmitter and receiver functionality, a typical part of the receiver section is the Automatic Gain Control (AGC) loop. An AGC loop is generally used to keep signal levels adequate throughout the signal path, to avoid saturating any part of the receiver whilst maximizing a signal-to-noise ratio required for its optimum operating conditions. The AGC loop circuitry and any associated algorithm works by measuring power levels of received signals at the receiver output, checking if they are within desired limits, and if power levels of received signals are not within desired limits, using that information to update the gain controls of the various signal-processing blocks in the receiver path.
Normally, the AGC loop uses a slow-reacting algorithm: the power measurement is done over a relatively long frame of data, and the gain controls are updated shortly before the next signal/item of data/frame is received. The assumption is that any changes in signal amplitude are slower than the AGC loop response time. However, this is not always the case. In a number of scenarios, in particular in wireless communication applications, a desired signal is processed at the same time as a large undesired interferer. If the interferer has a large rise in amplitude, it can easily saturate the receiver chain, potentially causing a temporary loss of the desired signal, which may not be corrected until the next frame of data is received. Depending on how long the AGC loop takes to recover from this condition, the receiver may lose the communication link. If the received data is part of a voice call, this may cause the call to be dropped. In conventional implementations, the receiver section is designed to avoid any signal characteristics that the AGC loop cannot handle. This requires a more conservative level plan, which may for example assign extra headroom for the various blocks in the signal chain. Ultimately, this translates into more stringent dynamic-range requirements and higher power consumption.
Dependent upon where in the receiver chain the AGC loop is located, the AGC loop may contain an analog-to-digital converter (ADC). An ADC is a device that converts a continuous physical quantity (usually voltage) to a digital number that represents the quantity's amplitude. The conversion involves quantization of the input, so it necessarily introduces a small amount of error. Instead of performing a single conversion, an ADC often performs the conversions (for example “samples” the input) periodically. The result is a sequence of digital values that have converted a continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal. An ADC may also provide an isolated measurement such as an electronic device that converts an input analog voltage or current to a digital number proportional to the magnitude of the voltage or current.
FIG. 1 illustrates a part of a receiver section 100 comprising an AGC loop. A Programmable Gain Amplifier (PGA) 105 represents the combined gain controls of the signal-conditioning blocks that precede the ADC 110. As an example, a receiver section may include a low-noise amplifier, a mixer, and a baseband filter before the ADC, and all of these blocks typically have such gain controls. The AGC loop 100 works to keep signal levels at the output 125 within optimum operation limits.
In order to do this, the AGC loop contains a digital filter 115 to filter the digitized signal output from the ADC 110. The output of the digital filter 115 is input to a filter and power measurement function 120, which outputs the filtered, digitized signal at output 125, as well as applying the filtered, digitized signal to an overload detection function 130. The overload detection function 130 then determines by how much to adjust the PGA 105 and provides a feedback automatic gain control signal 135.
Normally, the lower limit at the output 125 is selected to maintain a desired minimum signal-to-noise ratio, whilst the upper limit is set at a level that is safely below saturation. If the signal power is too low, the AGC loop 100 gradually increases the gain of the PGA 105 until the signal power is above the lower limit. If the signal power is too large, the AGC decreases the gain in the PGA 105 until it is below the upper limit.
An example of the signal behaviour of the circuit of FIG. 1 is shown in the waveform timing diagram 200 of FIG. 2. As illustrated, if the upper limit of the ADC input 205 is set too close to saturation, or if an unexpectedly large increase in signal power happens too quickly, the signal 220 from the PGA may be too large and saturate the ADC as shown at time T1 in period 215. Due to the time required for the AGC loop to determine that the signal power became too large, corrective action is only taken at time T2. Until then, throughout time period 215, any desired small signal component on top of the large signal is lost due to the ADC clipping 225 of the ADC input signal 220, as shown in the filter output waveform 210.
An additional complication may happen when the ADC is an oversampled delta-sigma converter, as illustrated in the waveform timing diagram 300 of FIG. 3 showing an alternative signal behaviour of the circuit of FIG. 1. As illustrated, if the upper limit of the ADC input 305 is set too close to saturation, or if an unexpectedly large increase in signal power happens too quickly, the signal 320 from the PGA may be too large and saturate the ADC as shown at time T1 in period 315. Due to the time required for the AGC loop to determine that the signal power became too large, corrective action is only taken at time T2. However, typically an oversampled delta-sigma ADC does not saturate with the simple clamping behaviour shown in FIG. 2. Instead, the oversampled delta-sigma ADC becomes unstable, and may require a reset of its internal integrator states to return to normal operation. However, as it attempts to recover, if the large input signal condition has not been removed, the ADC will repeatedly cycle between reset and recovery, as shown in the filter output waveform 310, and the resulting output may look ambiguous with regard to repetitive clipping 325 due to the AGC overload detection.
Thus, a need exists for an improved automatic gain control loop, for example with an ADC, an integrated circuit, electronic device (such as a wireless communication unit) and method of operation.